Dual-material mandrel for epitaxial crystal growth on silicon

ABSTRACT

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor devices and relates more specifically to multiple gate field effect transistors.

BACKGROUND OF THE DISCLOSURE

Multiple gate field effect transistors (FETs) are metal-oxide-semiconductor field effect transistors (MOSFETs) that incorporate more than one gate into a single device. A finFET is a specific type of multiple gate FET in which the conducting channel is wrapped by a thin fin forming the body of the device. The effective channel length of the device in this case is determined by the thickness of the fin (measured from source to drain). The wrap-around structure of the gate provides improved electrical control over the channel, and thus helps mitigate leakage current and other short-channel effects.

SUMMARY OF THE DISCLOSURE

In one example, a method for fabricating a semiconductor device includes etching a layer of silicon to form a plurality of fins and growing layers of a semiconductor material directly on sidewalls of the plurality of fins, wherein the semiconductor material and surfaces of the sidewalls have different crystalline properties.

In another example, a method for fabricating a semiconductor device includes depositing a buried oxide layer directly upon a substrate, depositing a silicon-on-insulator layer directly upon the buried oxide layer, and depositing a hard mask directly upon the silicon-on-insulator layer, where the hard mask comprises a first material layer deposited directly upon the silicon-on-insulator layer and a second material layer deposited directly upon the first material layer, and where the first material layer and the second material layer are formed from different materials. The hard mask is patterned to create a plurality of fins, and the silicon-on-insulator layer is etched in a manner that removes portions of the silicon-on-insulator layer not residing directly beneath the plurality of fins. A plurality of spacers is formed along exposed surfaces of the silicon-on-insulator layer, and a surface oxide is deposited over the plurality of spacers, where surface oxide fills in spaces between the plurality of fins. The second material layer of the hard mask and the plurality of spacers are removed in a manner that is selective to the first material layer of the hard mask and to the silicon on insulator layer, and the removal exposes sidewalls of the silicon-on-insulator layer. A semiconductor material is grown directly on the sidewalls of the silicon-on-insulator layer, where the semiconductor material is a different material from the material of the silicon-on-insulator layer. The surface oxide, the first material layer of the hard mask, and the silicon-on-insulator layer are removed in a manner that is selective to the semiconductor material.

In another example, a semiconductor device includes a plurality of fins comprising silicon. A layer of a semiconductor material is grown directly on a sidewall of at least one fin of the fins. The semiconductor material and the surface of fin have different crystalline properties.

BRIEF DESCRIPTION OF THE DRAWINGS

The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

FIGS. 1A-1H illustrate a semiconductor device during various stages of a first fabrication process performed according to examples of the present disclosure;

FIG. 2 illustrates a top view of a first example of a semiconductor device fabricated according to the process illustrated in FIGS. 1A-1H; and

FIG. 3 illustrates a top view of a first example of a semiconductor device fabricated according to the process illustrated in FIGS. 1A-1H.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures.

DETAILED DESCRIPTION

In one example, a dual-material mandrel for epitaxial crystal growth on silicon is disclosed. Semiconductor materials such as Groups III-V materials have been used to form transistors including finFET devices. These materials are typically difficult to obtain in bulk crystal form, and often must be grown on substrates. However, the differences in the crystalline properties of the semiconductor film and the substrate surface (e.g., different lattice constants) complicate growth of the semiconductor materials. Thick buffers deposited between the substrate surface and the semiconductor materials can facilitate growth; however, they also take up space on a device whose dimensions are already very limited without improving device operation.

Examples of the present disclosure provide a dual-material mandrel for epitaxial crystal growth on silicon that eliminates the need for a thick buffer at the substrate/semiconductor device interface. In one example, a hard mask comprising two material layers formed from different materials (e.g., an oxide and a nitride) is used to pattern a layer of crystalline silicon. A first of the material layers is removed to create trenches in which a semiconductor material, such as a Group III/V, Group II/IV, or Group IV semiconductor material can be grown directly onto the sidewalls of the patterned silicon, without the need for a buffer in between the silicon and the semiconductor material. The second of the material layers constrains the growth of the semiconductor material to the silicon sidewalls and is removed after the semiconductor material has been grown.

FIGS. 1A-1H illustrate a semiconductor device 100 during various stages of a first fabrication process performed according to examples of the present disclosure. As such, when viewed in sequence, 1A-1H also serve as a flow diagram for the first fabrication process. In particular, FIGS. 1A-1H illustrate cross sectional views of the semiconductor device 100 during the various stages of the first fabrication process.

Referring to FIG. 1A, one example of the semiconductor device 100 begins as a wafer or substrate 102, formed, for example, from bulk silicon (Si), a Group III-V material, a Group III-V material on silicon, or other semiconductor materials. In one example, the crystal orientation of the top surface of the substrate 102 (i.e., the surface upon which the rest of the structure of the semiconductor device 100 is built) is defined by a Miller index of (100) or (110). A buried oxide layer 104, formed, for example, by bonding or high energy oxygen implantation, is bonded directly on the wafer 102. A silicon-on-insulator (SOI) layer 106 is bonded directly on the buried oxide layer 104. In one example, the silicon of the SOI layer 106 has a crystalline orientation. In one example, the crystal orientation of the top surface of the SOI layer 106 is defined by a Miller index that is different from the Miller index defining the crystal orientation of the top surface of the substrate 102. For instance, if the crystal orientation of the top surface of the substrate 102 is defined by a Miller index of (100), the crystal orientation of the top surface of the SOI layer 106 may be defined by a Miller index of (110).

As illustrated in FIG. 1B, a mandrel or hard mask is next deposited directly on the SOI layer 106. The hard mask comprises a first material layer 108 and a second material layer 110 formed from two different materials. For instance, the first material layer 108 may be formed from an oxide, while the second material layer 110 may be formed from a nitride. Next, the first material layer 108 and the second material layer 110 of the hard mask are patterned to create a plurality of “fins.” Any number of fins may be created as a result of this patterning process, and the spacing between the individual fins is variable. Patterning of the first material layer 108 and the second material layer 110 involves etching the first material layer 108 and the second material layer 110 down to the SOI layer 106, and may further involve the deposition of additional layers of material, such as additional masks or other sacrificial materials (not shown), that are removed in the process of creating the structure illustrated in FIG. 1B. In one example, the patterning of the first material layer 108 and the second material layer 110 results in fins whose sidewalls are aligned to the crystal plane of the SOI layer 106 that is defined by a Miler index of (111), although other crystal orientations are also possible.

As illustrated in FIG. 1C, the SOI layer 106 is next etched down to the buried oxide layer 104. In one example, the etching of the SOI layer 106 is a wet etch or reactive ion etch (RIE) process. As illustrated, the portions of the SOI layer 106 that reside below the hard mask remain after the etching, and form the lower portions of the “fins” that were created by the patterning of the hard mask in FIG. 1B. In one example, the etching of the SOI layer 106 cuts into the silicon of the SOI such that the exposed surface of the SOI layer 106 is aligned in a crystal orientation that is defined by a Miler index of (111).

As illustrated in FIG. 1D, a plurality of spacers 1121-112 n (hereinafter collectively referred to as “spacers 112”) is next formed along the sidewalls of the fins. The spacers 112 thus contact the SOI layer 106 and the first material layer 108 and the second material layer 110 of the hard mask. In one example, the spacers 112 are formed from the same material as the second material layer 110 of the hard mask, e.g., from a nitride.

As illustrated in FIG. 1E, a surface oxide layer 114 is next deposited over the semiconductor device 100. The surface oxide layer 114 directly contacts the second material layer 110 of the hard mask, the spacers 112, and the buried oxide layer 104 and fills in the spaces between the fins. The surface oxide layer 114 is then planarized. As illustrated, planarization of the surface oxide layer 114 may additionally result in the planarization of portions of the spacers 112 and the second material layer 110 of the hard mask.

As illustrated in FIG. 1F, the second material layer 110 of the hard mask and the spacers 112 are next removed. In one example, removal of the second material layer 110 of the hard mask and the spacers 112 is performed using an etch process that is selective to (i.e., does not remove) the portions of the buried oxide layer 104, surface oxide layer 114, and the SOI layer 106 residing beneath the second material layer 110 of the hard mask and the spacers 112. Thus, the removal of the second material layer 110 of the hard mask and the spacers 112 results in a plurality of trenches 1161-116 n (hereinafter collectively referred to as “trenches 116”) being formed around the fins, in the areas where the spacers 112 used to be. This exposes the sidewalls of the fins (i.e., the sidewalls of the SOI layer 106 and the first material layer 108 of the hard mask).

As illustrated in FIG. 1G, semiconductor channels 1181-118 n (hereinafter collectively referred to as “semiconductor channels 118”) are next grown epitaxially directly on the sidewalls of the fins, i.e., in the trenches 116. In one example, growth of the semiconductor channels 118 is limited to the sidewalls of the SOI layer 106; thus, the semiconductor channels 118 directly contact the buried oxide layer 104 and the SOI layer 106 and do not extend to the first material layer 108 of the hard mask. The semiconductor channels 118 are formed from a semiconductor material having different properties from the sidewall surfaces of the SOI layer 106 (e.g., different lattice constants) but the same crystal orientation. In one example, the semiconductor channels 118 are formed from a Group III/V, Group II/IV, or Group IV semiconductor, such as indium gallium arsenide (InGaAs).

As illustrated in FIG. 1H, the surface oxide layer 114, the first material layer 108 of the hard mask, and the SOI 106 are next removed. In one example, the surface oxide layer 114, the second material layer 108 of the hard mask, and the SOI 106 are removed using an etch process, such as a xenon fluoride gas etch or a tetramethylammonium hydroxide wet anisotropic etch. As illustrated, the etching is selective to (i.e., does not remove) the epitaxially grown semiconductor channels 118.

The resultant semiconductor channels 118 may form the conducting channels of a finFET device. The finFet device may be an N-type device (NFET) or a P-type device (PFET). Thus, Groups III-V semiconductor channels may be grown directly on a silicon surface having a different crystalline structure, without the use of a thick buffer. Thus, device space is not wasted on buffers that provide no operational advantage. In the case of a PFET, a narrower version of the SOI layer 106 can be used as is to form the dual material fins.

Thus, the disclosed dual-material mandrel or hard mask eliminates the need for a thick buffer at the substrate/semiconductor device interface during fabrication of the semiconductor device 100. The only template needed to grow the semiconductor channels 118 is the SOI layer 106, which is small and thin relative to the typical buffer (which can be several pm thick and wide).

The process illustrated in FIGS. 1A-1H may be used to fabricate semiconductor channels in a plurality of different patterns upon the buried oxide layer, including one- and two-dimensional patterns. FIG. 2, for example, illustrates a top view of a first example of a semiconductor device 200 fabricated according to the process illustrated in FIGS. 1A-1H. In particular, FIG. 2 illustrates a semiconductor device 200 in which the semiconductor channels have been fabricated into a one-dimensional pattern. The buried oxide layer 202 is visible from the top, as are the semiconductor channels 2041-204 m (hereinafter collectively referred to as “semiconductor channels 204”), which are arranged in a set of parallel continuous lines. The arrangement illustrated in FIG. 2 is obtained by performing the process illustrated in FIGS. 1A-1H along only one of the x and y dimensions of the substrate.

FIG. 3 illustrates a top view of a first example of a semiconductor device 300 fabricated according to the process illustrated in FIGS. 1A-1H. In particular, FIG. 3 illustrates a semiconductor device 300 in which the semiconductor channels have been fabricated into a two-dimensional pattern. The buried oxide layer 302 is visible from the top, as are the semiconductor channels 3041-304 k (hereinafter collectively referred to as “semiconductor channels 304”), which are arranged in a rectangular matrix. The arrangement illustrated in FIG. 3 is obtained by performing the process illustrated in FIGS. 1A-1H along both of the x and y dimensions of the substrate.

Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings. 

What is claimed is:
 1. A field effect transistor, comprising: a semiconductor substrate; a buried oxide layer bonded directly on the semiconductor substrate; a plurality of silicon fins bonded directly on the buried oxide layer; and a layer of a semiconductor material grown directly on a sidewall of at least one fin of the plurality of silicon fins, wherein the semiconductor material and a surface of the at least one fin have different crystalline properties, but the same crystal orientation.
 2. The field effect transistor of claim 1, wherein crystal orientations of top surfaces of the plurality of silicon fins are different than a crystal orientation of a top surface of the semiconductor substrate.
 3. The field effect transistor of claim 1, wherein a crystal orientation of a top surface of the semiconductor substrate is defined by a Miller index of (100) or (110).
 4. The field effect transistor of claim 1, wherein the sidewall is aligned to a crystal plane of the at least one fin that is defined by a Miller index of (111).
 5. The field effect transistor of claim 1, wherein the semiconductor material is a Group III/V material.
 6. The field effect transistor of claim 1, wherein the semiconductor material is a Group II/VI material.
 7. The field effect transistor of claim 1, wherein the semiconductor material is a Group IV material.
 8. The field effect transistor of claim 1, wherein the field effect transistor is a finFET device.
 9. The field effect transistor of claim 8, wherein the layer of the semiconductor material forms a conducting channel of the finFET device. 